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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/KhandelwalS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ankur_Srivastava_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vishal_Khandelwal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1231996.1232002>
foaf:homepage <https://doi.org/10.1145/1231996.1232002>
dc:identifier DBLP conf/ispd/KhandelwalS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1231996.1232002 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ankur_Srivastava_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vishal_Khandelwal>
swrc:pages 11-18 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/KhandelwalS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/KhandelwalS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2007.html#KhandelwalS07>
rdfs:seeAlso <https://doi.org/10.1145/1231996.1232002>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject gate sizing, post-silicon tunability, stochastic optimization, timing optimization, variability (xsd:string)
dc:title Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document