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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/LuHES03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bing_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gary_Ellis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Haihua_Su>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F640000.640037>
foaf:homepage <https://doi.org/10.1145/640000.640037>
dc:identifier DBLP conf/ispd/LuHES03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F640000.640037 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Process variation aware clock tree routing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bing_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gary_Ellis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Haihua_Su>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
swrc:pages 174-181 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/LuHES03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/LuHES03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2003.html#LuHES03>
rdfs:seeAlso <https://doi.org/10.1145/640000.640037>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject VLSI, clock tree synthesis, interconnect, physical design (xsd:string)
dc:title Process variation aware clock tree routing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document