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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/RajaramP06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Z._Pan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1123008.1123038>
foaf:homepage <https://doi.org/10.1145/1123008.1123038>
dc:identifier DBLP conf/ispd/RajaramP06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1123008.1123038 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Variation tolerant buffered clock network synthesis with cross links. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Z._Pan>
swrc:pages 157-164 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/RajaramP06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/RajaramP06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2006.html#RajaramP06>
rdfs:seeAlso <https://doi.org/10.1145/1123008.1123038>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject VLSI CAD, clock network, non-tree clocks, physical design (xsd:string)
dc:title Variation tolerant buffered clock network synthesis with cross links. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document