[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/ShahETH07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alper_Halbutogullari>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeegar_Tilak_Shah>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeff_Trull>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marius_Evers>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1231996.1232010>
foaf:homepage <https://doi.org/10.1145/1231996.1232010>
dc:identifier DBLP conf/ispd/ShahETH07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1231996.1232010 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alper_Halbutogullari>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeegar_Tilak_Shah>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeff_Trull>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marius_Evers>
swrc:pages 67-74 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/ShahETH07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/ShahETH07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2007.html#ShahETH07>
rdfs:seeAlso <https://doi.org/10.1145/1231996.1232010>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject EDA, leakage power, low-power design, microprocessor, multi-VTH, optimization, sizing, timing (xsd:string)
dc:title Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document