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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/ShelarP10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marek_Patyra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1735023.1735060>
foaf:homepage <https://doi.org/10.1145/1735023.1735060>
dc:identifier DBLP conf/ispd/ShelarP10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1735023.1735060 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Impact of local interconnects on timing and power in a high performance microprocessor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marek_Patyra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
swrc:pages 145-152 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/ShelarP10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/ShelarP10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2010.html#ShelarP10>
rdfs:seeAlso <https://doi.org/10.1145/1735023.1735060>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject CAD, delay, interconnects, microprocessor, power (xsd:string)
dc:title Impact of local interconnects on timing and power in a high performance microprocessor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document