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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/ShelarSWS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prashant_Saxena>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xinning_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1055137.1055166>
foaf:homepage <https://doi.org/10.1145/1055137.1055166>
dc:identifier DBLP conf/ispd/ShelarSWS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1055137.1055166 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label An efficient technology mapping algorithm targeting routing congestion under delay constraints. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prashant_Saxena>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rupesh_S._Shelar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xinning_Wang>
swrc:pages 137-144 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/ShelarSWS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/ShelarSWS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2005.html#ShelarSWS05>
rdfs:seeAlso <https://doi.org/10.1145/1055137.1055166>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject logic synthesis, routing congestion, technology mapping (xsd:string)
dc:title An efficient technology mapping algorithm targeting routing congestion under delay constraints. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document