An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ispd/SuSN02
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2002
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An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
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ASICs, adjoint sensitivity, decoupling capacitor, optimization, placement, power grid noise
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An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
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