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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/ToyonagaKYT00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Atsushi_Takahashi_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keiichi_Kurokawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Toyonaga>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takuya_Yasui>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F332357.332393>
foaf:homepage <https://doi.org/10.1145/332357.332393>
dc:identifier DBLP conf/ispd/ToyonagaKYT00 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F332357.332393 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label A practical clock tree synthesis for semi-synchronous circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Atsushi_Takahashi_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keiichi_Kurokawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Toyonaga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takuya_Yasui>
swrc:pages 159-164 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/ToyonagaKYT00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/ToyonagaKYT00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2000.html#ToyonagaKYT00>
rdfs:seeAlso <https://doi.org/10.1145/332357.332393>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject clock scheduling, clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree (xsd:string)
dc:title A practical clock tree synthesis for semi-synchronous circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document