Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ispd/TsengC08
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Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
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buffer insertion, low power, voltage island architecture
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Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
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