An effective BIST architecture for power-gating mechanisms in low-power SRAMs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isqed/BosioDGVZ16
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An effective BIST architecture for power-gating mechanisms in low-power SRAMs.
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An effective BIST architecture for power-gating mechanisms in low-power SRAMs.
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