Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isqed/CardosoRMRR08
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Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
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Transistor networks, logic synthesis, BDDs, Logical effort
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Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
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