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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/ChuangJPK03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ruchir_Puri>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2003.1194724>
foaf:homepage <https://doi.org/10.1109/ISQED.2003.1194724>
dc:identifier DBLP conf/isqed/ChuangJPK03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2003.1194724 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ruchir_Puri>
swrc:pages 153-158 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/ChuangJPK03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/ChuangJPK03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2003.html#ChuangJPK03>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2003.1194724>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document