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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/Lin01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rong_Lin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2001.915251>
foaf:homepage <https://doi.org/10.1109/ISQED.2001.915251>
dc:identifier DBLP conf/isqed/Lin01 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2001.915251 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rong_Lin>
swrc:pages 325-330 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/Lin01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/Lin01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2001.html#Lin01>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2001.915251>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:subject IP design, array multiplier, inner product processor, matrix multiplier, polynomial evaluation, run-time reconfigurable architecture, SOC. (xsd:string)
dc:title Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document