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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/LinSVD06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ing-Chao_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nagu_R._Dhanwada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Narayanan_Vijaykrishnan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suresh_Srinivasan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2006.138>
foaf:homepage <https://doi.org/10.1109/ISQED.2006.138>
dc:identifier DBLP conf/isqed/LinSVD06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2006.138 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ing-Chao_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nagu_R._Dhanwada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Narayanan_Vijaykrishnan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suresh_Srinivasan>
swrc:pages 775-780 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/LinSVD06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/LinSVD06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2006.html#LinSVD06>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2006.138>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document