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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/LiuZH07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tong_Zhang_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Liu_0016>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2007.146>
foaf:homepage <https://doi.org/10.1109/ISQED.2007.146>
dc:identifier DBLP conf/isqed/LiuZH07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2007.146 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tong_Zhang_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Liu_0016>
swrc:pages 749-754 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/LiuZH07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/LiuZH07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2007.html#LiuZH07>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2007.146>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document