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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/MukhopadhyayKKLJCR05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jae-Joon_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Hsien_Lo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2005.77>
foaf:homepage <https://doi.org/10.1109/ISQED.2005.77>
dc:identifier DBLP conf/isqed/MukhopadhyayKKLJCR05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2005.77 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jae-Joon_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Hsien_Lo>
swrc:pages 410-415 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISQED.2005.77>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document