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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/PoulosYVL14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Veneris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bao_Le>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Shen_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zissis_Poulos>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2014.6783384>
foaf:homepage <https://doi.org/10.1109/ISQED.2014.6783384>
dc:identifier DBLP conf/isqed/PoulosYVL14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2014.6783384 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Simulation and satisfiability guided counter-example triage for RTL design debugging. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Veneris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bao_Le>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Shen_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zissis_Poulos>
swrc:pages 618-624 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/PoulosYVL14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/PoulosYVL14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2014.html#PoulosYVL14>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2014.6783384>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Simulation and satisfiability guided counter-example triage for RTL design debugging. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document