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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/QiZKRS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jan_M._Rabaey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matthew_M._Ziegler>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mircea_R._Stan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_V._Kosonocky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhenyu_Qi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2007.105>
foaf:homepage <https://doi.org/10.1109/ISQED.2007.105>
dc:identifier DBLP conf/isqed/QiZKRS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2007.105 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Multi-Dimensional Circuit and Micro-Architecture Level Optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jan_M._Rabaey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matthew_M._Ziegler>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mircea_R._Stan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_V._Kosonocky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhenyu_Qi>
swrc:pages 275-280 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/QiZKRS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/QiZKRS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2007.html#QiZKRS07>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2007.105>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Multi-Dimensional Circuit and Micro-Architecture Level Optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document