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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/ReddyJSM12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/G._K._Reddy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jawar_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kapil_Jainwal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2012.6187539>
foaf:homepage <https://doi.org/10.1109/ISQED.2012.6187539>
dc:identifier DBLP conf/isqed/ReddyJSM12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2012.6187539 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label Process variation tolerant 9T SRAM bitcell design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/G._K._Reddy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jawar_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kapil_Jainwal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
swrc:pages 493-497 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/ReddyJSM12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/ReddyJSM12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2012.html#ReddyJSM12>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2012.6187539>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title Process variation tolerant 9T SRAM bitcell design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document