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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/RomaDSPP05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Carlo_Roma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guido_De_Sandre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Pasotti>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Poles>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pierluigi_Daglio>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2005.62>
foaf:homepage <https://doi.org/10.1109/ISQED.2005.62>
dc:identifier DBLP conf/isqed/RomaDSPP05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2005.62 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Carlo_Roma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guido_De_Sandre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Pasotti>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Poles>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pierluigi_Daglio>
swrc:pages 107-112 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/RomaDSPP05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/RomaDSPP05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2005.html#RomaDSPP05>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2005.62>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document