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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/SellierPBCFBF08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexis_Farcy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bertrand_Borot>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Boeuf>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean-Michel_Portal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manuel_Sellier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Richard_Ferrant>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steve_Colquhoun>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2008.4479784>
foaf:homepage <https://doi.org/10.1109/ISQED.2008.4479784>
dc:identifier DBLP conf/isqed/SellierPBCFBF08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2008.4479784 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexis_Farcy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bertrand_Borot>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Boeuf>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean-Michel_Portal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manuel_Sellier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Richard_Ferrant>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steve_Colquhoun>
swrc:pages 492-497 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/SellierPBCFBF08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/SellierPBCFBF08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2008.html#SellierPBCFBF08>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2008.4479784>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:subject Predictive SPICE Modeling, Interconnect Delay, Interconnect Resistance, Buffer Insertion (xsd:string)
dc:title Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document