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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/SinghAMP10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dilip_S._Aswar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jawar_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2010.5450397>
foaf:homepage <https://doi.org/10.1109/ISQED.2010.5450397>
dc:identifier DBLP conf/isqed/SinghAMP10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2010.5450397 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dilip_S._Aswar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jawar_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
swrc:pages 131-138 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/SinghAMP10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/SinghAMP10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2010.html#SinghAMP10>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2010.5450397>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:title A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document