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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isqed/YelamarthiC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-In_Henry_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kumar_Yelamarthi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISQED.2008.4479715>
foaf:homepage <https://doi.org/10.1109/ISQED.2008.4479715>
dc:identifier DBLP conf/isqed/YelamarthiC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISQED.2008.4479715 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-In_Henry_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kumar_Yelamarthi>
swrc:pages 143-147 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isqed/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isqed/YelamarthiC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isqed/YelamarthiC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isqed/isqed2008.html#YelamarthiC08>
rdfs:seeAlso <https://doi.org/10.1109/ISQED.2008.4479715>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isqed>
dc:subject dynamic circuits, transistor sizing, timing optimization, process variations, binary-to-thermometer decoder, binary adders. (xsd:string)
dc:title Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document