A fully pipelined implementation of Monte Carlo based SSTA on FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isqed/YuasaTOS11
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A fully pipelined implementation of Monte Carlo based SSTA on FPGAs.
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A fully pipelined implementation of Monte Carlo based SSTA on FPGAs.
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