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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/issac/BihanRS09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Casey_E._Stella>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Bihan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Maurice_Rojas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1576702.1576711>
foaf:homepage <https://doi.org/10.1145/1576702.1576711>
dc:identifier DBLP conf/issac/BihanRS09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1576702.1576711 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Faster real feasibility via circuit discriminants. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Casey_E._Stella>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Bihan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Maurice_Rojas>
swrc:pages 39-46 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/issac/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/issac/BihanRS09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/issac/BihanRS09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/issac/issac2009.html#BihanRS09>
rdfs:seeAlso <https://doi.org/10.1145/1576702.1576711>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/issac>
dc:subject discriminant chamber, feasibility, linear forms in logarithms, polynomial-time, real, sparse (xsd:string)
dc:title Faster real feasibility via circuit discriminants. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document