19.1 A 0.5-to-9.5GHz 1.2¬Ķs-lock-time fractional-N DPLL with ¬Ī1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
19.1 A 0.5-to-9.5GHz 1.2¬Ķs-lock-time fractional-N DPLL with ¬Ī1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
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19.1 A 0.5-to-9.5GHz 1.2¬Ķs-lock-time fractional-N DPLL with ¬Ī1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
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