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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isscc/BolSMHXFDSF19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Charlotte_Frenkel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Stas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ludovic_Moreau>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maxime_Schramme>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pengcheng_Xu_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Remi_Dekimpe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Haine>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSCC.2019.8662293>
foaf:homepage <https://doi.org/10.1109/ISSCC.2019.8662293>
dc:identifier DBLP conf/isscc/BolSMHXFDSF19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSCC.2019.8662293 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label A 40-to-80MHz Sub-4őľW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20őľs Wake-Up From Deep Fully Retentive Sleep Mode. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Charlotte_Frenkel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Bol>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Stas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ludovic_Moreau>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maxime_Schramme>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pengcheng_Xu_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Remi_Dekimpe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Haine>
swrc:pages 322-324 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isscc/2019>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isscc/isscc2019.html#BolSMHXFDSF19>
rdfs:seeAlso <https://doi.org/10.1109/ISSCC.2019.8662293>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isscc>
dc:title A 40-to-80MHz Sub-4őľW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20őľs Wake-Up From Deep Fully Retentive Sleep Mode. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document