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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isscc/DavisBHCSRPKW13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Rodko>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Diana_M._Henderson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_Davis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_Bunce>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pradip_Patel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_J._Knips>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tobias_Werner_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uma_Srinivasan_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuen_H._Chan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSCC.2013.6487754>
foaf:homepage <https://doi.org/10.1109/ISSCC.2013.6487754>
dc:identifier DBLP conf/isscc/DavisBHCSRPKW13 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSCC.2013.6487754 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
rdfs:label 7GHz L1 cache SRAMs for the 32nm zEnterprise‚ĄĘ EC12 processor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Rodko>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Diana_M._Henderson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_Davis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_Bunce>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pradip_Patel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_J._Knips>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tobias_Werner_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uma_Srinivasan_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuen_H._Chan>
swrc:pages 324-325 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isscc/2013>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isscc/DavisBHCSRPKW13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isscc/DavisBHCSRPKW13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#DavisBHCSRPKW13>
rdfs:seeAlso <https://doi.org/10.1109/ISSCC.2013.6487754>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isscc>
dc:title 7GHz L1 cache SRAMs for the 32nm zEnterprise‚ĄĘ EC12 processor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document