A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Pradeep_Trivedi>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shaishav_Desai>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Vincent_Von_Kanael>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FISSCC.2007.373417>
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dc:identifier	DBLP conf/isscc/DesaiTK07 (xsd:string)
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rdfs:label	A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Shaishav_Desai>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Vincent_Von_Kanael>
swrc:pages	308-605 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/ISSCC.2007.373417>
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dc:title	A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. (xsd:string)
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