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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isscc/FujiwaraLPLHLLC19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Han_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chih-Yu_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hidehiro_Fujiwara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hsien-Yu_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hung-Jen_Liao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jhon-Jhy_Liaw>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kao-Cheng_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Po-Yi_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yen-Huei_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSCC.2019.8662415>
foaf:homepage <https://doi.org/10.1109/ISSCC.2019.8662415>
dc:identifier DBLP conf/isscc/FujiwaraLPLHLLC19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSCC.2019.8662415 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Han_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chih-Yu_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hidehiro_Fujiwara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hsien-Yu_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hung-Jen_Liao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jhon-Jhy_Liaw>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jonathan_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kao-Cheng_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Po-Yi_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yen-Huei_Chen>
swrc:pages 390-392 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isscc/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isscc/FujiwaraLPLHLLC19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isscc/FujiwaraLPLHLLC19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isscc/isscc2019.html#FujiwaraLPLHLLC19>
rdfs:seeAlso <https://doi.org/10.1109/ISSCC.2019.8662415>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isscc>
dc:title A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document