15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Koji_Nii>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Masaru_Haraguchi>
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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tsung-Yung_Jonathan_Chang>
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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yu-Hao_Hsu>
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Tsung-Yung_Jonathan_Chang>
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dc:title	15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. (xsd:string)
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