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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isscc/KimKSPPBDRBOWGK24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anandkumar_Mahadevan_Pillai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayush_Shrivastava>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Clifford_Ong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daeyeon_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eric_Karl>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gwanghyeon_Baek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gyusung_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kunal_Bannore>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muktadir_Rahman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tri_Doan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaofei_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yusung_Kim_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zheng_Guo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSCC49657.2024.10454501>
foaf:homepage <https://doi.org/10.1109/ISSCC49657.2024.10454501>
dc:identifier DBLP conf/isscc/KimKSPPBDRBOWGK24 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSCC49657.2024.10454501 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
rdfs:label 15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anandkumar_Mahadevan_Pillai>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Clifford_Ong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daeyeon_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eric_Karl>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gwanghyeon_Baek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gyusung_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kunal_Bannore>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muktadir_Rahman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tri_Doan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaofei_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yusung_Kim_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zheng_Guo>
swrc:pages 278-280 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISSCC49657.2024.10454501>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isscc>
dc:title 15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document