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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isscc/LeeKHY11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexandra_M._Kern>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyung-Jin_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ian_A._Young>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sami_Hyvonen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSCC.2011.5746235>
foaf:homepage <https://doi.org/10.1109/ISSCC.2011.5746235>
dc:identifier DBLP conf/isscc/LeeKHY11 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSCC.2011.5746235 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
rdfs:label A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexandra_M._Kern>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyung-Jin_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ian_A._Young>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sami_Hyvonen>
swrc:pages 96-97 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isscc/2011>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isscc/LeeKHY11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isscc/LeeKHY11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isscc/isscc2011.html#LeeKHY11>
rdfs:seeAlso <https://doi.org/10.1109/ISSCC.2011.5746235>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isscc>
dc:title A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document