Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isscc/TeradaONKKY09
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Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
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Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit.
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