11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2őľm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2őľm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
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11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2őľm Pitch with up to 40% Energy Reduction at Iso-Area Footprint.
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