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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isss/AraujoM95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guido_Araujo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F224486.224493>
foaf:homepage <https://doi.org/10.1145/224486.224493>
dc:identifier DBLP conf/isss/AraujoM95 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F224486.224493 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Optimal code generation for embedded memory non-homogeneous register architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guido_Araujo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
swrc:pages 36-41 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isss/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isss/AraujoM95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isss/AraujoM95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isss/isss1995.html#AraujoM95>
rdfs:seeAlso <https://doi.org/10.1145/224486.224493>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isss>
dc:subject TMS320C25 processor, [1, /spl infin/] model, computational complexity, computer architecture, embedded memory nonhomogeneous register architectures, expression trees, graph theory, instruction selection, instruction set architecture, instruction sets, microprocessor chips, optimal code generation, optimisation, processor scheduling, register allocation, register transfer graph, scheduling, storage allocation, structural representation, sufficient conditions (xsd:string)
dc:title Optimal code generation for embedded memory non-homogeneous register architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document