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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isss/BeniniVCM96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Claudionor_Jos%E2%88%9A%C2%A9_Nunes_Coelho_Jr.>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Patrick_Vuillod>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISSS.1996.565878>
foaf:homepage <https://doi.org/10.1109/ISSS.1996.565878>
dc:identifier DBLP conf/isss/BeniniVCM96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISSS.1996.565878 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Claudionor_Jos%E2%88%9A%C2%A9_Nunes_Coelho_Jr.>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Patrick_Vuillod>
swrc:pages 57- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isss/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isss/BeniniVCM96/dblp>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isss/isss1996.html#BeniniVCM96>
rdfs:seeAlso <https://doi.org/10.1109/ISSS.1996.565878>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isss>
dc:subject High level synthesis, low power, finite state machines, gated clocks. (xsd:string)
dc:title Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document