System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isss/ChatterjeeEMPCP02
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System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
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design space, embedded systems, power-performance trade-offs, voltage/frequency scaling
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System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
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