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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isss/JerrayaLMRG02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Amine_Jerraya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Damien_Lyonnard>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ferid_Gharsalli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Rousseau_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Samy_Meftali>
foaf:homepage <http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FISSS.2002.1227147>
foaf:homepage <https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227147>
dc:identifier DBLP conf/isss/JerrayaLMRG02 (xsd:string)
dc:identifier DOI doi.ieeecomputersociety.org%2F10.1109%2FISSS.2002.1227147 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahmed_Amine_Jerraya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Damien_Lyonnard>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ferid_Gharsalli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Rousseau_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Samy_Meftali>
swrc:pages 26-31 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isss/2002>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isss/isss2002.html#JerrayaLMRG02>
rdfs:seeAlso <https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227147>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isss>
dc:subject embedded memory, memory access, memory wrapper generation, system-on-chip (xsd:string)
dc:title Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document