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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/ChengCL04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Che-Yu_Liao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuo-Hsing_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shun-Wen_Cheng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2004.1339539>
foaf:homepage <https://doi.org/10.1109/ISVLSI.2004.1339539>
dc:identifier DBLP conf/isvlsi/ChengCL04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISVLSI.2004.1339539 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Che-Yu_Liao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuo-Hsing_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shun-Wen_Cheng>
swrc:pages 233-236 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/ChengCL04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isvlsi/ChengCL04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#ChengCL04>
rdfs:seeAlso <https://doi.org/10.1109/ISVLSI.2004.1339539>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isvlsi>
dc:subject CPL, conditional sum adder, low-threshold voltage, low-voltage, differential-end, VLSI design (xsd:string)
dc:title 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document