Architecture for Dual-Mode Quadruple Precision Floating Point Adder.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/JaiswalVS15
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/JaiswalVS15
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/B._Sharat_Chandra_Varma_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hayden_Kwok-Hay_So
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Manish_Kumar_Jaiswal
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2015.70
>
foaf:
homepage
<
https://doi.org/10.1109/ISVLSI.2015.70
>
dc:
identifier
DBLP conf/isvlsi/JaiswalVS15
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FISVLSI.2015.70
(xsd:string)
dcterms:
issued
2015
(xsd:gYear)
rdfs:
label
Architecture for Dual-Mode Quadruple Precision Floating Point Adder.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/B._Sharat_Chandra_Varma_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hayden_Kwok-Hay_So
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Manish_Kumar_Jaiswal
>
swrc:
pages
249-254
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2015
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/JaiswalVS15/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/isvlsi/JaiswalVS15
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2015.html#JaiswalVS15
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ISVLSI.2015.70
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/isvlsi
>
dc:
title
Architecture for Dual-Mode Quadruple Precision Floating Point Adder.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document