Wire Length Distribution Model Considering Core Utilization for System on Chip.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/KyogokuINUOM05
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/KyogokuINUOM05
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hidenari_Nakashima
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Junpei_Inoue
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kazuya_Masu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kenichi_Okada
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takanori_Kyogoku
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takumi_Uezono
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2005.76
>
foaf:
homepage
<
https://doi.org/10.1109/ISVLSI.2005.76
>
dc:
identifier
DBLP conf/isvlsi/KyogokuINUOM05
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FISVLSI.2005.76
(xsd:string)
dcterms:
issued
2005
(xsd:gYear)
rdfs:
label
Wire Length Distribution Model Considering Core Utilization for System on Chip.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hidenari_Nakashima
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Junpei_Inoue
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kazuya_Masu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kenichi_Okada
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takanori_Kyogoku
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takumi_Uezono
>
swrc:
pages
276-277
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2005
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/KyogokuINUOM05/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/isvlsi/KyogokuINUOM05
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2005.html#KyogokuINUOM05
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ISVLSI.2005.76
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/isvlsi
>
dc:
subject
Wire Length Distribution, core utilization, SoC, layout-area allocation
(xsd:string)
dc:
title
Wire Length Distribution Model Considering Core Utilization for System on Chip.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document