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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/MailiSWQD05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_Maili>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Christian_Steger>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Damian_Dalton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Reinhold_Weiss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rob_Quigley>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2005.61>
foaf:homepage <https://doi.org/10.1109/ISVLSI.2005.61>
dc:identifier DBLP conf/isvlsi/MailiSWQD05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISVLSI.2005.61 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_Maili>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Christian_Steger>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Damian_Dalton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Reinhold_Weiss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rob_Quigley>
swrc:pages 290-291 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/MailiSWQD05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isvlsi/MailiSWQD05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2005.html#MailiSWQD05>
rdfs:seeAlso <https://doi.org/10.1109/ISVLSI.2005.61>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isvlsi>
dc:title Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document