All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/M._B._Srinivas>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Swathi_Ramasahayam>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2009.41>
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dcterms:issued	2009 (xsd:gYear)
rdfs:label	All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2009.html#RamasahayamS09>
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dc:title	All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. (xsd:string)
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