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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/RanganathanNH06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nagarajan_Ranganathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Narender_Hanchate>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ravi_Namballa>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2006.27>
foaf:homepage <https://doi.org/10.1109/ISVLSI.2006.27>
dc:identifier DBLP conf/isvlsi/RanganathanNH06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISVLSI.2006.27 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nagarajan_Ranganathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Narender_Hanchate>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ravi_Namballa>
swrc:pages 329-334 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/RanganathanNH06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isvlsi/RanganathanNH06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#RanganathanNH06>
rdfs:seeAlso <https://doi.org/10.1109/ISVLSI.2006.27>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isvlsi>
dc:title CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document