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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isvlsi/RosielloFPS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Angelo_P._E._Rosiello>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Davide_Pandini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donatella_Sciuto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Ferrandi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2007.5>
foaf:homepage <https://doi.org/10.1109/ISVLSI.2007.5>
dc:identifier DBLP conf/isvlsi/RosielloFPS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISVLSI.2007.5 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Angelo_P._E._Rosiello>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Davide_Pandini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donatella_Sciuto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Ferrandi>
swrc:pages 92-97 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isvlsi/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isvlsi/RosielloFPS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isvlsi/RosielloFPS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2007.html#RosielloFPS07>
rdfs:seeAlso <https://doi.org/10.1109/ISVLSI.2007.5>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isvlsi>
dc:title A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document