An Optimized BIST Architecture for FPGA Look-Up Table Testing. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FISVLSI.2006.24>
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dcterms:issued	2006 (xsd:gYear)
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swrc:pages	420-421 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#YarandiAN06>
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dc:title	An Optimized BIST Architecture for FPGA Look-Up Table Testing. (xsd:string)
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