Consequences of port restrictions on testing two-port memories.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/itc/HamdiouiG98
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Consequences of port restrictions on testing two-port memories.
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Multi-port memories, single-port memories, memory fault models, weak faults, march tests, test length, fault coverage, read-only and write-only ports
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Consequences of port restrictions on testing two-port memories.
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