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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ivsw/BreschMAMH17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Adrien_Michelet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cyril_Bresch>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_H%E2%88%9A%C2%A9ly>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laurent_Amato>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Meyer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIVSW.2017.8031545>
foaf:homepage <https://doi.org/10.1109/IVSW.2017.8031545>
dc:identifier DBLP conf/ivsw/BreschMAMH17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIVSW.2017.8031545 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label A red team blue team approach towards a secure processor design with hardware shadow stack. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Adrien_Michelet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cyril_Bresch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_H%E2%88%9A%C2%A9ly>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laurent_Amato>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Meyer>
swrc:pages 57-62 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ivsw/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ivsw/BreschMAMH17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ivsw/BreschMAMH17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ivsw/ivsw2017.html#BreschMAMH17>
rdfs:seeAlso <https://doi.org/10.1109/IVSW.2017.8031545>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ivsw>
dc:title A red team blue team approach towards a secure processor design with hardware shadow stack. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document