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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ivsw/SiddiquiSBBPS19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ali_Shuja_Siddiqui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fareena_Saqib>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Geraldine_Shirley>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Girija_Bhagwat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jim_Plusquellic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shreya_Bendre>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIVSW.2019.8854418>
foaf:homepage <https://doi.org/10.1109/IVSW.2019.8854418>
dc:identifier DBLP conf/ivsw/SiddiquiSBBPS19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIVSW.2019.8854418 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Secure Design Flow of FPGA Based RISC-V Implementation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ali_Shuja_Siddiqui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fareena_Saqib>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Geraldine_Shirley>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Girija_Bhagwat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jim_Plusquellic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shreya_Bendre>
swrc:pages 37-42 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ivsw/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ivsw/SiddiquiSBBPS19/dblp>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ivsw/ivsw2019.html#SiddiquiSBBPS19>
rdfs:seeAlso <https://doi.org/10.1109/IVSW.2019.8854418>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ivsw>
dc:title Secure Design Flow of FPGA Based RISC-V Implementation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document